A significant trend throughout IC development has been to try to increase the “yield rate” of semiconductor fabrication systems. The yield rate refers to the percentage of usable IC's produced by a fabrication system compared to the total number attempted. Similarly, the yield rate may refer to the percentage of usable IC's obtained from an average semiconductor wafer that is processed through the fabrication system. A semiconductor wafer is essentially a thin disc of highly purified semiconductor material on which many IC's are fabricated together and then separated for individual packaging.
Significant factors that can negatively impact the yield rate are the number and size of defects in the wafer. Defects may include cracks, crazes (i.e. microscopic cracks), chips, flakes, scratches, marks, missing/broken edges and particle and residue contamination, among others. Defects are particularly detrimental to the yield rate when they occur on the top surface of the wafer, since the top surface is the region where the IC's are formed on the wafer. Of historically lesser concern have been any other areas of the wafer, such as the bottom surface and the edge, or bevel, of the wafer. Since these areas are further from the formation of the IC's, any defects therein have been considered to have less of an impact on the yield rate for the IC's. Thus, many wafer-inspection and defect-detection techniques have been developed to inspect for defects in the top surface of wafers; whereas, comparatively few techniques have been developed to inspect for defects elsewhere on the wafers.
Until recently, wafer edge inspection has primarily been performed by manual visual inspection by a worker in the fabrication plant. A high-resolution camera may be used to generate an image of the wafer edge on a monitor, which the worker manually views for defects. This edge inspection technique is in stark contrast to the various complex computerized image-analysis techniques, among other inspection techniques, that have been developed to inspect the top surface of the wafers. Recent developments in non-visual inspection of wafer edges have merely included emitter/detector pairs for ultrasonic waves and laser/light beams for limited detection of cracks and breaks at the edge. These techniques may be used in combination with visual inspection to confirm the presence of any defects in the wafer edge. Detailed image-analysis techniques have not been used for wafer edge defect detection, since it has been commonly considered unnecessary to do so.
Additionally, current non-visual wafer edge inspection techniques may record data plots (not images), which a worker may review for indications of defects or a computer may analyze for possible defects. Though the data may be stored for a time, the purpose of the data is generally for immediate pass/fail analysis of the wafer, so the wafer may be passed on for further processing, discarded as unusable or rerouted for rework or repair.
It is with respect to these and other considerations that the present invention has evolved.